FIG. 1 shows a schematic of a typical pinned photodiode four transistor (4T) active pixel, of the type used in image sensors. The active pixel comprises a pinned photodiode PD, a transfer gate TG, a reset transistor M1, a buffer amplifier M2 and a select transistor M3. A pinned photodiode PD is selectively connected to a sense node FD via the transfer gate TG. The transfer gate TG is controlled by a control line Tx. The reset transistor M1 connects between the sense node FD and a supply line VDD. Transistor M1 is controlled by a signal RESET. Transistor M2 is also connected to the sense node FD and is configured as a source-follower amplifier which acts as a buffer amplifier for the signal generated by the photodiode PD. A transistor M3 connects between the output of the buffer amplifier M2 and an output bus and is controlled by a signal provided by control line SELECT. In operation, photocharge is accumulated by the photodiode PD. Before readout of the photocharge, the floating diffusion (FD) is reset through the reset switch M1. The reset level is read out through the source follower M2 and selection transistor M3 to the column bus. Then the charges accumulated in the photodiode PD are transferred through the transfer transistor to the floating diffusion FD. The signal level is again read out through the source follower M2 and selection transistor M3.
FIG. 2 shows a first way of arranging a plurality of the pixels of FIG. 1 to form a pixel array suitable for fabrication in semiconductor material. Each photodiode PD has its own transfer gate, reset transistor, buffer amplifier and read transistor. The reset transistor, buffer amplifier and read transistor will be called readout circuitry. Each pixel is controlled by three horizontal control lines (SELECT, RESET AND TRANSFER (Tx)). Each control line operates all of the pixels in a single row of the pixel array. A pixel building block of the array is shown as item 100, and comprises a photodiode 101, readout circuitry 102 and control lines. The pixel building block 100 is replicated across an area to form the pixel array. Looking at the resulting array, photodiode 111 is served by readout circuitry 112; photodiode 113 is served by readout circuitry 114, and so on. This architecture requires the routing of three horizontal metal lines per pixel pitch. Other types of pixel are known which use more transistors and these may have more, or fewer, control lines and readout lines. For example, an array which is capable of global shutter operation requires more transistors and control lines.
One known way of increasing the density of pixels in an array is to arrange for a number of photodiodes to share the readout circuitry. In this way, each photodiode does not require the readout circuitry shown in FIG. 1. FIG. 3 schematically shows two photodiodes PD1, PD2 which share readout circuitry 20. Reset transistor M1, buffer amplifier M2 and select switch M3 are used, on a time-shared basis, to readout a value representing the amount of charge accumulated by each photodiode. The values are read consecutively through a common column bus. Each photodiode has a dedicated transfer gate TG1, TG2 to transfer accumulated charge to the sense node when that photodiode is read.
A known layout of a two-shared pixel is shown in FIG. 4. A pixel “building block”, or unit cell, is shown as item 200. This is the basic element which is repeated multiple times to form the array. The pixel building block 200 has a reset and select line, two transfer lines and a single column bus (not shown). Looking at the resulting array, photodiodes 211 and 212 are served by readout circuitry 213; photodiodes 214 and 215 are served by readout circuitry 216, and so on. The advantage of this sharing architecture is that less readout circuitry 213, 216 is required in the pixel array, which results in more area for the photodiodes. A further advantage is that only two metal lines need to be routed per pixel pitch, compared with three lines for the non-shared architecture. The capacitive load of readout junctions on the column bus is also reduced by a factor of two.
A particular disadvantage of this architecture is that it has an asymmetrical pixel configuration, which means that the photodiodes are optically different (e.g. 211 vs 212, 214 vs 215 and so on). The photoresponse of the photodiodes can typically differ significantly when the chief ray angle is not perpendicular. Impinging photons are reflected/absorbed differently depending on the metal routing (which is different for the different photodiodes) and angle of incidence. Many applications require a symmetrical Modulation Transfer Function (MTF) and similar cross-talk behaviour for all of the pixels, and cannot tolerate asymmetry.
Examples of shared-pixel architectures are described in: U.S. Pat. No. 6,107,655 (2×2 pixel sharing); U.S. Pat. No. 6,352,869 (2×2 pixel sharing); U.S. Pat. No. 7,057,150; US 2006/0256221 A1; U.S. Pat. No. 6,043,478; and US 2006/0208163 A1.
The present invention seeks to provide an alternative way of providing a shared pixel architecture.